Typical methods to fabricate a butt-joined passive waveguide structure involves etching past the active region of the active device to grow the desired waveguide. FIG. 1 shows typical active passive butt joint structure 100. On n-InP base wafer 110, active region 150 is surrounded by separate confinement heterostructure (SCH) layers 145 and 155. P-InP cladding layer 130 and n-InP cladding layer 120 border on SCH layers 155 and 145, respectively. Passive Q-waveguide core 190 is sandwiched between n-InP layer 180 and p-InP layer 185. P-InP layer 160 serves as a cladding layer and p(+)-InGaAs layer 170 serves as a contact layer. To minimize mode mismatch losses at the interface between active region 150 and passive Q-waveguide core 190, the position and composition of passive Q-waveguide core 190 are appropriately selected. The presence of n-InP layer 180 and p-InP layer 185 on either side of passive Q-waveguide core 190 implies that the parasitic capacitance at the interface is determined by the thickness of passive Q-waveguide layer 190 core.
However, when attempting to make a low parasitic electro-absorption (EA) modulator with passive waveguide there is an optimization problem because the parasitic capacitance value is determined by the thickness of passive Q-waveguide core 190. As noted above, the thickness of passive Q-waveguide core 190 is constrained by mode matching issues. These issues typically arise when a passive waveguide needs to be butt joined to an active device requiring low parasitic capacitance such as is typically required in making optical integrated structures.